In the manufacture of semiconductor chips, a silicon wafer or other substrate is exposed to a variety of different processes in different processing chambers. The chambers may expose the wafer to a number of different chemical and physical processes whereby minute integrated circuits are created on the substrate. Layers of materials which make up the integrated circuit are created by processes including chemical vapor deposition, physical vapor deposition, epitaxial growth, and the like. Some of the layers of material are patterned using photoresist masks and wet or dry etching techniques. The substrates may be silicon, gallium arsenide, indium phosphide, glass, or other appropriate materials.
In these manufacturing processes, plasma may be used for depositing or etching various material layers. Plasma processing offers many advantages over thermal processing. For example, plasma enhanced chemical vapor deposition (PECVD) allows deposition processes to be performed at lower temperatures and at higher deposition rates than in analogous thermal processes. PECVD therefore allows material to be deposited at lower temperatures.
The processing chambers used in these processes typically include a substrate support, pedestal, or chuck disposed therein to support the substrate during processing. In some processes, the pedestal may include an embedded heater adapted to control the temperature of the substrate and/or provide elevated temperatures that may be used in the process.
HAR (High Aspect Ratio) plasma etch uses a significantly higher bias power to achieve bending free profiles. In order to support HAR for dielectric etching, the power may be increased to 20 KW, which brings significant impacts on an ESC (Electrostatic Chuck). Many current ESC designs cannot survive such a high voltage which comes as a direct result of a high bias power. Holes designed into an ESC may suffer in particular. Moreover, an ESC may experience bond failures in the lift pin area when excess radicals erode the bonds. Another impact is that the ESC surface temperature changes at a higher rate. The heating of the ESC surface is directly proportional to the applied RF plasma power. The heat may also be a result of bond failure. In addition bowing of the wafer carried on the ESC and the charge build up on the wafer also makes wafer de-chucking more difficult.
Common processes use an ESC to hold a wafer with 2 MHz 6.5 KW plasma power applied to the wafer for etching applications. High aspect ratio (e.g. 100:1) applications use much higher plasma powers. An ESC is described herein that operates with a low frequency high power plasma voltage to generate a high wafer bias. The higher power will increase failures of the ESC due to the dielectric breaking down and due to plasma ignition in gas holes that are designed into the ESC.